Abstract: Our second attempt at using stixels for navigation and exploring its computational properties. This time we integrate with our egocircle representation and explore two different approaches to realizing local-global navigation. Computational scaling and navigation benchmark tests indicate that stixel navigation can be used across a variety of onboard computing platforms for mobile robots.

Abstract: Our second attempt at integrating the PiPS concept with a local-global navigation scheme. This time we used Timed Elastic Bands (TEB) as the base local planner. Modifying TEB using our egocentric approach leads to egoTEB. A world, grid-based approach has a computational cost that scales with the area of the local grid, whereas the egocircle approach scales with the boundaries. Thus rather than scale quadratically, it scales linearly with regards to the sensing footprint.

Abstract: Our first attempt at integrating the PiPS concept with a local-global navigation scheme. It modified the DWA planner in the ROS Move Base package. The procedure required defining the egocircle representation and using it as a body-frame collision and cost-map reference for planning. Both PiPS and the egocircle lead to linear scaling in sensor throughput and collision checking, which is confirmed through computational profiling and compared to other collision checking methods.

Abstract: Stixels are an intermediate stereo representation for the world. The basic version models the world as sticks rising from the ground plane, which makes it a potentially lossy representation (overhanging or floating obstacles might be missed). As an intermediate representation, it can be used for ego-centric navigation.

Abstract: Explores the use of perception-space, e.g., a visual representation space, for collision checking during navigation through an unknown environment. Employing the Marr's concept of the 2.5D representation, the collision checking approach speeds up the time to collision-checking to permit low latency or real-time navigation on limited compute hardware, as well as high performance hardware.